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| GIM>Investigación>Publicaciones |
| PUBLICACIONES en las que participa: "Eugenio Villar" ordenadas por línea de investigación |
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| Diseño y verificación de sistemas electrónicos para comunicaciones |
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Artur Wegele, Pablo Peñil, Eugenio Villar, Wolfgang Mueller, Da He, Fabian Mischkalla, et. al.
"Updated frameworks"
Deliverable D4.5 the FP7-216807 SATURN Project. 2010-12 |
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A. Antón, Eugenio Villar, D.B. de Vries & S.M. H. de Groot
"Design and functional description of a sender and receiver for ATM adaptation layer protocols"
XIII Design of Circuits and Integrated Systems Conference (DCIS98). Madrid. 1998-11 |
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Ll. Terés, Y. Torroja, S. Olcoz, Eugenio Villar
"VHDL: Lenguaje estándar de Diseño Electrónico"
McGraw Hill. 1998-01 |
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Eugenio Villar, Pablo Pedro Sánchez
"Síntesis"
VHDL: Lenguaje estándar de diseño electrónico
McGraw-Hill. 1998-01 |
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A. Antón, Eugenio Villar, D.B. de Vries, S. M. H. de Groot.
"Flexible architecture for processing ATM adaptation layer protocols (AAL1-5)"
IEEE Journal of Electrical Engineering, V.49, N.3-4, pp. 70-75. 1998-01 |
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P. Tabuenca, Eugenio Villar
"An algorithm for clock cycle selection in behavioral synthesis"
Journal of Systems Architecture, V.44, N.9-10, North-Holland, pp. 773-786. 1998-01 |
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A. Antón, Eugenio Villar, D. B. de Vries, S.M. Heemstra de Groot
"Design and functional description of a receiver for ATM Adaptation Layer Protocols"
6th HCM BELDESIGN Workshop. Aveiro (Portugal). 1997-10 |
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A. Antón, Eugenio Villar, S.M. Heemstra de Groot, D. B. de Vries
"Flexible Architecture for Processing ATM Adaptation Layer Protocols (AAL1-5)"
First Electronic Circuits and Systems Conference (ECS97). Bratislava (Slovakia). 1997-09 |
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H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, Eugenio Villar
"Design of a Flexible Architecture for Processing ATM Adaptation Layer Protocols"
ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing. Mierlo (The Netherlands). 1996-11 |
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H.W.A. Teunissen, D. B. de Vries, S.M. Heemstra de Groot, A. Antón, Eugenio Villar
"A Flexible Architecture for Processing ATM Adaptation Layer Protocols"
4th HCM BELSIGN Workshop, Santander. 1996-10 |
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M. Imai, Eugenio Villar
"ASPDAC 1995: HDL synthesizability and interoperability"
IEEE Design & Test of Computers. Panel Summaries, pp 3-4. 1996-04 |
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W. Ecker, Eugenio Villar
"VHDL multi-wait descriptions for synthesis"
Working Conference of VHDL Forum for CAD in Europe, Dresden Germany, pp 59-69. 1996-04 |
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H.W.A. Teunissen, D.B. de Vries, S.M. Heemstra de Groot, A. Antón, Eugenio Villar
"Design of a flexible architecture for processing ATM adaptation layer protocols"
CTIT Technical Report series, N. 96-40 University of Twente, The Netherlands. 1996-01 |
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M. Selz, W. Ecker, Eugenio Villar
"VHDL synthesis description portability: The need for Level-x synthesis subsets"
Journal of System Architecture 42, North-Holland, pp 105-116. 1996-01 |
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Eugenio Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 2nd Part"
The VHDL Newsletter, No. 20, pp.1 and 12. 1995-12 |
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Eugenio Villar
"The Level-0 VHDL Synthesis Syntax and Semantics - 1st Part"
The VHDL Newsletter, No. 19, pp. 10-11. 1995-10 |
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J. L. Barreda, I. Hidalgo, Víctor Fernández, Pablo Pedro Sánchez, Eugenio Villar
"Fault Modeling in VITAL"
Proceedings of the Workshop on Libraries, Component Modeling, and Quality Assurance. Nantes, France. 1995-04 |
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M. Selz, W. Ecker, Eugenio Villar
"VHDL synthesis description portability: The need for Level-x Synthesis Subsets"
Spring´95 Working Conference of the VHDL Forum for CAD in Europe. Nantes (France). 1995-04 |
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Pedro Tabuenca, Eugenio Villar, L. Muñoz, R. Sanz
"Estudio de viabilidad de la implementación ASIC"
Documento Final del proyecto GAME "Análisis de viabilidad de un ASIC para chasis de baja". 1995-03 |
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C. Delgado Kloos, Eugenio Villar
"VHDL: El lenguaje estándar de diseño electrónico"
Novática. 1995-01 |
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| Métodos de test de circuitos integrados digitales y mixtos |
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J. L. Barreda, Pablo Pedro Sánchez, Eugenio Villar
"Current fault modeling in VITAL"
VHDL International User´s Forum. Santa Clara, CA, USA. 1996-02 |
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I. González, Eugenio Villar, Salvador Bracho
"Inserción automática de estructuras BIST en entornos de síntesis usando VHDL"
X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS95). Zaragoza. 1995-11 |
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| Diseño y verificación de sistemas embebidos HW/SW |
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Eugenio Villar, Javier Merino, Héctor Posadas, R. Henia (Thales TRT), L. Rioux (Thales TRT)
"Mega-Modeling of complex, distributed, heterogeneous CPS systems"
Microprocessors and Microsystems (accepted). 2020-08 |
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Eugenio Villar
"Megamodeling of complex, distributed, heterogeneous CPS systems"
Summer School on Cyber-Physical Systems and Internet-of-Things - CPS&IoT’2019, Budva, Montenegro, 2019. 2019-09 |
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Álvaro Díaz, Eugenio Villar, Pablo Pedro Sánchez
"Integrated Framework for Reusable Multi-Level Embedded System Verification"
Work-in-Progress Session, DAC, San Francisco. 2018-06 |
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Eugenio Villar
"Model-Driven Analysis of Security, Reliability, Test, Privacy, Safety and Trust of IoE Services
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Surrealist Workshop of the IEEE European Test Symposium, Bremen, Germany. 2018-05 |
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Eugenio Villar
"Model-Driven Analysis and Design of IoT Systems"
DATE Workshop W06: Embedded Software for Industrial IoTs, ESIIT 2018. 2018-03 |
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Álvaro Díaz, Eugenio Villar, Daniel Peña
"Short and Long Distance Marker Detection Technique in Outdoor and Indoor Environments for Embedded Systems"
XXXI Conference on Design of Circuits and Integrated Systems, DCIS 2017. 2017-11 |
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Fernando Herrera, J. Medina, Eugenio Villar
"Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design approach"
in Soonhoi Ha and Jürgen Teich (Eds): "Handbook of Hardware/Software Codesign", Springer. 2017-09 |
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J. Medina (UC-ISTR), Eugenio Villar
"Towards MARTE++: An Enhanced UML-based Language to Model and Analyse Real-Time and Embedded Systems for the IoT Age"
Forum on Specification and Design Languages, Verona, 2017. 2017-09 |
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H. Hassan, L. T. Yang, J. Xue, Eugenio Villar
"Special issue on: “Heterogeneous architectures for Cyber-physical
systems (HACPS)”"
Microprocessors and Microsystems N.52, Elsevier, pp. 333–334. 2017-07 |
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K. Grüttner, R. Görgen, S. Schreiner, Fernando Herrera, Pablo Peñil, J. Medina, Eugenio Villar, et al.
"CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties"
Microprocessors and Microsystems, V.51, pp. 39-55, doi=10.1016/j.micpro.2017.03.012. 2017-06 |
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F. Mallet, Eugenio Villar, Fernando Herrera
"MARTE for CPS and CPSoS"
in S. Nakajima, J.P. Talpin, M. Toyoshima and H. Yu (Eds.): "Cyber-Physical System Design from an Architecture Analysis Viewpoint: Communications of NII Shonan Meetings", Springer, pp.81-108, doi="10.1007/978-981-10-4436-6. 2017-05 |
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Eugenio Villar, Patricia Martínez
"Positioning System for Recreated Reality Applications based on high performance Video-Processing"
in A. Molnos, C. Fabre (Eds.):"Model-Implementation Fidelity in Cyber Physical System Design", pp.201-230, Springer. 2016-12 |
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Héctor Posadas, Eugenio Villar
"Using Professional Resources for Teaching Embedded SW Development"
Revista Iberoamericana de Tecnologias del Aprendizaje, V. 11, I. 4, IEEE, pp. 248 – 255. 2016-11 |
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R. Gorgen, K. Gruttner, Fernando Herrera, Pablo Peñil, J. Medina, Eugenio Villar, G. Palermo, W. Fornaciari, C. Brandolese, D. Gadioli, et. al.
"CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties "
19th Euromicro Conference on Digital System Design, DSD 2016, IEEE. 2016-09 |
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Pablo Peñil, Héctor Posadas, Julio Medina, Eugenio Villar
"UML-Based Single-Source Approach for Evaluation and optimization of Mixed-Critical Embedded Systems
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XXX Conference on Design of Circuits and Integrated Systems, DCIS 2015, IEEE. 2015-11 |
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